1. Field of the Invention
The present invention relates to a semiconductor device provided with multi-level interconnects and a manufacturing method thereof.
In particular, the invention relates to a semiconductor integrated circuit device having multi-level interconnects with low parasitic capacitance and operated at high speed of several hundreds of MHz or more and a manufacturing method thereof.
2. Description of Related Art
In a semiconductor integrated circuit device operated at high speed of several hundreds of MHz or more, signal propagation delay due to parasitic capacitance in multi-level interconnects is significant.
FIG. 1 is a schematical plan view of multi-level interconnects. Reference numeral 1 denotes a semiconductor substrate, 4 a lower level interconnect, 14 a via, and 24 a higher level interconnect. Normally, adjacent level interconnects are laid out in directions crossing perpendicularly to each other. This means that the area to face each other is small between higher level and lower level interconnects. As a result, parasitic capacitance between adjacent interconnects in a level is generally larger than that between interconnects in different levels, and exert more influence on signal propagation delay. Accordingly, attempts have been made to reduce parasitic capacitance between the adjacent interconnects in a level by replacing the insulating film material (silicon oxide film (specific dielectric constant: kxcx9c4) and silicon nitride film (kxcx9c7)) between adjacent interconnects in a level with insulating film material with lower dielectric constant.
Methylsiloxane type film is one of the low dielectric constant film (kxcx9cabout 3 or lower). This is a film having Sixe2x80x94CH3 bond and Sixe2x80x94Oxe2x80x94Si bond as main components. In addition, Sixe2x80x94H bond or Sixe2x80x94Cxe2x80x94Si bond may be contained. There are the following methods to form the film: spin-coating and chemical vapor deposition (CVD). In the spin-coating, oligomer solution containing methylsiloxane (spin-on glass (SOG)) is deposited by spin-coating, and then is cured. In the CVD, a gas containing Sixe2x80x94CH3 bond reacts with oxidizing gas in a CVD chamber. The advantageous feature of methylsiloxane type film is that it has high heat-resistant property and is stable in heat treatment (up to 450xc2x0 C.) in the manufacturing process of multi-level interconnects.
However, when high-pressure oxygen plasma treatment is performed on methysiloxane type film, the film is deteriorated due to oxygen radicals in the plasma and absorbs moisture, and the quality of the film such as electrical characteristics is deteriorated. For this reason, conventional type patterning method cannot be used, in which a resist mask is removed by high-pressure oxygen plasma treatment after transferring the pattern.
A first method to solve this problem is disclosed in Japanese Patent Application 151102/1988, which describes the use of low-pressure oxygen plasma to remove the resist. According to this method, deterioration of the quality of methylsiloxane type film is suppressed. This is because oxygen ions in the low-pressure oxygen plasma modify the surface of the methylsiloxane type film to fine silicon oxide, and this surface layer protects inner part of the film from oxygen radicals.
There is a second method to prevent deterioration of the quality when the resist is removed, and this is disclosed in JP-A-87502/1999. It is a method to transfer resist pattern to hard mask, and after removing the resist in advance, the methylsiloxane type film is etched using the hard mask.
FIG. 2 to FIG. 4 each represents a cross-sectional view showing of a manufacturing process to explain the second method. On a methylsiloxane type film 6, a hard mask material 8 such as silicon nitride is deposited. A silicon oxide film 27, and further, a resist 9 are formed on it, and the resist is patterned by lithography (FIG. 2). After etching the silicon oxide film 27 using the resist mask 9, the resist 9 is removed (FIG. 3). In this case, the methylsiloxane type film 6 is covered with the hard mask material 8, and it is not exposed to oxygen plasma, and hence, it is not deteriorated. After transferring the pattern to the hard mask 8, the silicon oxide film 27 is removed. Then, using the hard mask 8, the methylsiloxane type film 6 is patterned (FIG. 4).
According to the first method as described above, it is not possible to form a hole pattern or a trench pattern with high aspect ratio (depth over diameter or depth over trench width). When the aspect ratio increases, the number of ions impinging on the pattern side-wall surface is decreased. As a result, surface passivation layer is not formed on the methylsiloxane type film and its quality is deteriorated. In practical application, this method is effective only in the case where the aspect ratio  less than 3.
When the methylsiloxane type film is fabricated by the second method as described above, shoulder portion of the hard mask 8 collapses diagonally as shown in FIG. 4 (faceting). In case low resistance copper wire is used as the lower level interconnect 4, an etching stopper 5 on the surface of the interconnect must be etched (FIG. 5). As the etching stopper 5, silicon nitride film, silicon carbide film, etc. are used. Under the etching condition to etch the etching stopper 5, both the hard mask 8 and the methylsiloxane type film 6 are etched at the similar rate as the etching stopper 5. As a result, faceting of the hard mask 8 occurs more remarkably (FIG. 6). When there is a portion where the hard mask 8 completely disappears, faceting occurs on the methylsiloxane type film 6 underneath. Further, the faceting is expanded in argon sputter-etching, which is performed as pre-treatment (cleaning) of the next metal deposition (FIG. 7).
The first problem caused by the faceting is that sputtered dielectrics 98 are deposited on pattern bottom in case of argon sputter-etching, and this results in via-connection failure. The faceting prior to the sputter-etching increases the amount of the sputtered dielectrics, so increases the via-connection failure.
The second problem caused by the faceting is that buried metals 14 in the pattern are not completely separated from each other, and this causes short-circuit failure (FIG. 8).
It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant without causing via-connection failure and short circuit failure due to faceting even when lower level interconnects are covered with etching stopper.
According to an aspect of the method for manufacturing a semiconductor device of the present invention, inter-level dielectrics for forming holes for vias or trenches for interconnects are fabricated as layered films of a methylsiloxane type film and a different insulating film formed on the film, and the layered films are processed using a hard mask. As a result, hole pattern or trench pattern is transferred to the hard mask using a resist, and the resist is then removed. In this case, deterioration of the quality of the methylsiloxane type film can be prevented because the methylsiloxane type film is covered with the insulating film.
Also, when a hole or a trench is formed on the layered films, it is possible to prevent transfer of the faceting of the hard mask to the methylsiloxane type film because the insulating film is formed between the methylsiloxane type film and the hard mask. Thus, the first and the second problems as described above can be overcome. By setting the etching rate of the insulating film to ⅓ or less of that of the hard mask, the insulating film acts as a hard mask for the methylsiloxane type film, and the higher effects can be obtained. As an example of the material for the insulating film, it is effective to use silicon oxide film because it can suppress the increase of parasitic capacitance between the interconnects.
Further, in case the dual damascene process in which holes for vias or trenches for interconnects are formed at the same time, layered films of methylsiloxane type film, a different insulating film and a hard mask are deposited on the similar layered films, and then the hole and the trench are formed at the same time. In this case, the insulating film prevents quality deterioration caused by removal of the resist on the methylsiloxane type film under the insulating film, and also the transfer of the faceting of the hard mask to the methylsiloxane type film can be prevented. In case of the dual damascene process in which trench pattern is transferred to the higher level hard mask and hole pattern is transferred to the lower level hard mask, the resist used for patterning of the lower level hard mask is removed by low-pressure oxygen plasma treatment, and quality deterioration of the methylsiloxane type film formed on the lower level hard mask can be suppressed.
In case the etching stopper is formed on the lowermost layer of the inter-level dielectrics, the hard mask on the exposed portion is removed at the same time when the hole is formed on the etching stopper. As a result, it is possible to reduce parasitic capacitance between the multi-level interconnects.
According to an aspect of a semiconductor device of the present invention, inter-level dielectrics with dual damascene interconnects formed on it are made as layered films comprising a first methylsiloxane type film, a first insulating film, a hard mask, a second methylsiloxane type film, and a second insulating film in this order from below, and the manufacturing method as described above can be applied. The decrease of production yield caused by via-connection failure or short-circuit failure of multi-level interconnects can be prevented, and a semiconductor integrated circuit device to be operated at high speed of several hundreds of MHz or more can be manufactured at lower cost.
Other and further objects, features and advantages of the invention will appear more fully from the following description.